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1 ? fn9101.6 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL6218 precision single-phase buck pwm controller for intel mobile voltage positioning imvp-iv ? and imvp-iv+ ? the ISL6218 single-phase buck pwm control ic, with integrated half bridge gate driver, provides a precision voltage regulation system for advanced pentium-m microprocessors in notebook com puters. this control ic also features both input voltage f eed-forward and average current mode control for excellent dynamic response, ?loss-less? current sensing using mosfet r ds(on) , and user selectable switching frequencies from 250khz to 500khz per phase. the ISL6218 includes a 6-bit digital-to-analog converter (dac) that dynamically adjusts the core pwm output voltage from 0.700v to 1.708v in 16mv steps, and conforms to the intel imvp-iv ? mobile vid specification. the ISL6218 also has logic inputs to select active, deep sleep and deeper sleep modes of operation. a precision reference, remote sensing and proprietary architecture with integrated processor-mode compensated ?droop? provides excellent static and dynamic core voltage regulation. another feature of the ISL6218 ic controller is the internal pgood delay circuit that holds the pgood pin low for 3ms to 12ms after the vccp and vcc_mch regulators are within regulation. this pgood signal is masked during vid changes. output overvoltage and undervoltage are monitored and result in the converter latching off and pgood signal being held low. the overvoltage and undervoltage thresholds are 112% and 84% of the vid, deep or deepe r sleep setpoint. overcurrent protection featur es a 32 cycle overcurrent shutdown. pgood, overvoltage, undervoltage and overcurrent provide monitoring and protec tion for the microprocessor and power system. the ISL6218 ic is available in a 38 ld tssop and 40 ld qfn package. features ? imvp-iv ? compliant core regulator ? single-phase power conversion ? ?loss-less? current sensing for improved efficiency and reduced board area - optional discrete precision current sense resistor ? internal gate drive and boot-strap diode ? precision core voltage regulation - 0.8% system accuracy over-temperature ? 6-bit microprocessor voltage identification input ? programmable ?droop? and core voltage slew rate to comply with imvp-iv ? specification ? discontinuous mode of operation for increased light load efficiency in deep and deeper sleep mode ? direct interface with system logic (stp _cpu and dprslpvr) for deep and deeper sleep modes of operation ? easily programmable voltage setpoints for initial ?boot?, deep sleep and deeper sleep modes ? excellent dynamic response - combined voltage feed-forward and average current mode control ? overvoltage, undervoltage and overcurrent protection ? power-good output with internal blanking during vid and mode changes ? user programmable switching frequency of 250khz to 500khz ? pb-free plus anneal available (rohs compliant) ordering information part number part marking temp. range (c) package pkg. dwg # ISL6218cv* isl 6218cv -10 to +85 38 ld tssop m38.173 ISL6218cvz* (note) isl 6218cvz -10 to +85 38 ld tssop (pb-free) m38.173 ISL6218cvza* (note) isl 6218cvz -10 to +85 38 ld tssop (pb-free) m38.173 ISL6218crz* (note) isl62 18crz -10 to +85 40 ld 6x6 qfn (pb-free) l40.6x6 *add ?-t? suffix for tape and reel. please refe r to tb347 for details on reel specifications. note: intersil pb-free plus anneal products employ special pb-free material sets ; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb- free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet august 6, 2007
2 fn9101.6 august 6, 2007 pinouts ISL6218 (38 ld tssop) top view ISL6218 (40 ld qfn) top view 12 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 vdd dacout dsv fset nc en drsen dsen vid0 vid1 vid2 vid3 vid4 vid5 pgood ea+ comp fb soft 27 38 37 36 35 34 33 32 31 30 29 28 26 25 24 23 22 21 20 vbat isen phase ug boot vssp lg1 vddp nc nc nc nc nc nc vsen drsv stv ocset vss ISL6218 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 nc fset dsv dacout vdd vbat isen phase ug boot vssp lg vddp nc nc nc nc nc nc nc en drsen dsen vid0 vid1 vid2 vid3 vid4 vid5 pgood ea+ comp fb nc soft vss ocset stv drsv vsen ISL6218
3 fn9101.6 august 6, 2007 absolute maximum rati ngs thermal information supply voltage vdd, vddp . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7v battery voltage, vbat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+25v boot1 and ugate1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+33v phase1 and isen1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28v boot1 with respect to phase1 . . . . . . . . . . . . . . . . . . . . . . . . . +6.5v ugate1. . . . . . . . . . . . . . . . . . . . (phase1 - 0.3v) to (boot1 + 0.3v) all other pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd + 0.3v) recommended operating conditions supply voltage, vdd, vddp . . . . . . . . . . . . . . . . . . . . . . . +5v 5% battery voltage, vbat . . . . . . . . . . . . . . . . . . . . . . . . . +5.6v to 21v ambient temperature. . . . . . . . . . . . . . . . . . . . . . . . .-10c to +85c junction temperature . . . . . . . . . . . . . . . . . . . . . . .-10c to +125c thermal resistance (typical) ja (c/w) jc (c/w) tssop package (note 1) . . . . . . . . . . . . 72 n/a qfn package (notes 2, 3) . . . . . . . . . . . 32 4.5 maximum operating junction temperature. . . . . . . . . . . . . . +125c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 1. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 3. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 4. limits established by characteri zation and are not production tested. electrical specifications operating conditions: v dd = 5v, t a = -10c to +85c, unless otherwise specified. parameter test conditions min typ max units input supply power input supply current, i(vdd) en = 3.3v, dsen = 0, drsen = 0 - 1.4 - ma en = 0v - 1 - a por (power-on reset) threshold vdd rising 4.39 4.45 4.5 v vdd falling 4.10 4.20 4.37 v reference and dac system accuracy percent system deviation from programmed vid codes @ 1.356 -0.8 - 0.8 % dac (vid0 to vid5) input low voltage dac programming input low threshold voltage - - 0.3 v dac (vid0 to vid5) input high voltage dac programming input high threshold voltage 0.7 - - v maximum output voltage - 1.708 - v minimum output voltage -0.70- v channel generator frequency, f sw r fset = 243k, 1% 225 250 275 khz adjustment range 250 - 500 khz error amplifier dc gain - 100 - db gain-bandwidth product c l = 20pf - 18 - mhz slew rate c l = 20pf - 4.0 - v/s ISL6218
4 fn9101.6 august 6, 2007 isen full scale input current -32- a overcurrent threshold r ocset = 110k (see figure 10) - 54 - a soft-start current soft = 0v - 31 - a droop current isen = 32a 12.0 14 16.0 a gate driver ugate source resistance 500ma source current - 1 1.5 ugate source current (note 4) v ugate-phase = 2.5v - 2 - a ugate sink resistance 500ma sink current - 1 1.5 ugate sink current (note 4) v ugate-phase = 2.5v - 2 - a lgate source resistance 500ma source current - 1 1.5 lgate source current (note 4) v lgate = 2.5v - 2 - a lgate sink resistance 500ma sink current - 0.5 0.8 lgate sink current (note 4) v lgate = 2.5v - 4 - a bootstrap diode forward voltage vddp = 5v, forward bias current = 10ma 0.57 0.68 0.74 v power good monitor pgood sense current 2.43 - - ma pgood pull-down mosfet r ds(on) 56 63 82 undervoltage threshold (vsen/vref) vsen rising - 85.0 - % undervoltage threshold (vsen/vref) vsen falling - 84.0 - % pgood low output voltage i pgood = 4ma - 0.26 0.4 v logic threshold en, dsen , drsen low --1 v en, dsen , drsen high 2-- v protection overvoltage threshold (v sen /v ref )v sen rising - 112.0 - % delay time delay time from lgate falling to ugate rising vddp = 5v, boot to phase = 5v, ugate - phase = 1v, lgate = 1v 10 18 30 ns delay time from ugate falling to lgate rising vddp = 5v, boot to phase = 5v, ugate - phase = 1v, lgate = 1v 10 18 30 ns electrical specifications operating conditions: v dd = 5v, t a = -10c to +85c, unless otherwise specified. (continued) parameter test conditions min typ max units ISL6218
5 fn9101.6 august 6, 2007 functional pin description 38 ld tssop vdd this pin is used to connect +5v to the ic to supply all power necessary to operate the chip. the ic starts to operate when the voltage on this pin exceeds the rising por threshold and shuts down when the voltage on this pin drops below the falling por threshold. vddp this pin provides a low esr bypass connection to the internal gate drivers for the +5v source. pgood this pin is used as an input and an output and is tied to the vccp and vcc_mch pgood signals. during start-up, this pin is recognized as an input, and pr events further slewing of the output voltage from the ?boot? level until pgood from vccp and vcc_mch is enabled high. after start-up, this pin has an open drain output used to indicate the status of the core output voltage. this pin is pu lled low when the system output is outside of the regulation lim its. pgood includes a timer for power-on delay. en this pin is connected to the system signal vr_on and provides the enable/disable function for the pwm controller. ocset a resistor from this pin to ground sets the overcurrent protection threshold. the current from this pin should be between 10a and 25a (70k to 175k equivalent pull-down resistance). vsen this pin is used for remote sensing of the microprocessor core voltage. comp this pin provides connection to the error amplifier output. fb this pin is connected to the inverting input of the error amplifier. ea+ this pin is connected to the no n-inverting input of the error amplifier and is used for setting the ?droop? voltage. stv the voltage on this pin sets the initial start-up or ?boot? voltage. soft this pin programs the slew rate of vid changes, deep sleep and deeper sleep transitions, and soft-start after initializing. this pin is connected to ground via a capacitor, and to ea+ through an external ?droop? resistor. dsen this pin connects to system logic ?stp _cpu ? and enables deep sleep mode of operation. deep sleep is enabled when a logic low signal is detected on this pin. drsen this pin connects to system logic ?dprslpvr? and enables deeper sleep mode of operation when a logic high is detected on this pin. vbat voltage on this pin provides f eed-forward battery information that adjusts the oscillator ramp amplitude. fset a resistor from this pin to ground programs the switching frequency. isen this pin is used as current sense input from the converter channel phase node. dacout this pin provides access to the output of the digital-to- analog converter. dsv the voltage on this pin provides the setpoint for output voltage during deep sleep mode of operation. drsv the voltage on this pin provides the setpoint for output voltage during deeper sleep mode of operation. 12 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 vdd dacout dsv fset nc en drsen dsen vid0 vid1 vid2 vid3 vid4 vid5 pgood ea+ comp fb soft 27 38 37 36 35 34 33 32 31 30 29 28 26 25 24 23 22 21 20 vbat isen phase ug boot vssp lg vddp nc nc nc nc nc nc vsen drsv stv ocset vss ISL6218 ISL6218
6 fn9101.6 august 6, 2007 vid0, vid1, vid2, vid3, vid4, vid5 these pins are used as inputs to the 6-bit digital-to-analog converter (dac). vid0 is the le ast significant bit and vid5 is the most significant bit. ug this pin is the gate drive outpu t to the high side mosfets. lg this pin is the gate drive output to the low side mosfets. boot this pin is connected to the bootstrap capacitor for upper gate drive. phase this pin is connected to the phase node of the power channel. vssp this pin is the return for the lower gate drive and is connected to power ground. vss this pin provides connection for signal ground. typical application figure 1 shows a single-phase synchronous buck converter circuit used to provide ?core? voltage regulation for the intel pentium-m mobile processor using imvp-iv ? voltage positioning. the circuit shows pin connections for the ISL6218 pwm controller in the 38 ld tssop package. figure 1. typical application circuit fo r ISL6218 single-pha se pwm controller vdd dacout dsv fset nc en drsen dsen vid0 vid1 vid2 vid3 vid4 vid5 pgood ea+ comp fb soft vr_on dprslpvr stp _cpu vid pwrgd v battery +5vdc +5vdc +vcc_core ISL6218 tssop vbat isen phase ug boot vssp lg vddp nc nc nc nc nc nc vsen drsv stv ocset vss ISL6218
7 fn9101.6 august 6, 2007 block diagram i ocset power-on reset (por) + - e/a pwm pwm vdd fb fset + - clock and vid0 vid1 vid2 vid3 comp generator sawtooth vid4 en 1.3v + - i droop ocset vid d/a isen 1.75v vid5 soft vsen pgood ovp + - control and fault logic vbat 1.75v soft- start vsoft - + 88% rising 84% falling uv v core ref dsv drsv mux channel current sense three-state 32 count 112% rising 102% falling 32 count clock cycle ea+ dacout stv phase logic lg vssp vddp ug phase boot - + oc clock cycle i sen vddp 0.5 sample 2a 0.435 isen and hold dsen drsen vss ISL6218
8 fn9101.6 august 6, 2007 theory of operation initialization once the +5vdc supply voltage (as connected to the ISL6218 vdd pin) reaches the power-on reset (por) rising threshold, the pwm drive signals are held in ?three-state? or high impedance mode. this results in both the high side and low side mosfets being held off. once the supply voltage exceeds the por rising threshold, the controller will respond to a logic level high on the en pin and initiate the soft-start interv al. if the supply voltage drops below the por falling threshold, por shutdown is triggered and the pwm outputs are again driven to ?three-state?. the system signal, vr_on is di rectly connected to the en pin of the ISL6218. once the voltage on the en pin rises above 2.0v, the chip is enabled and soft-start begins. the en pin of the ISL6218 is also used to reset the ISL6218 for cases when an undervoltage or overcurrent fault condition has latched the ic off. toggling the state of this pin to a level below 1.0v will re-enable the ic. for the case of an overvoltage fault, the vdd pin must be reset. during start-up, the ISL6218 regulates to the voltage on the stv pin. this is referred to as the ?boot? voltage and is labeled vboot in figure 2. once power good signals are received from the vccp and vcc_mch regulators, the ISL6218 will capture the vid code and regulate, within 3ms to 12ms, to this command voltage. the pgood pin of the ISL6218 is both an input and an output and is further described in ?fault protection? on page 13. soft-start interval refer to figure 2 and figure 4. once vdd rises above the por rising threshold and the en pin voltage is above the threshold of 2.0v, a soft-start interval is initiated. the voltage on the ea+ pin is the reference voltage for the regulator. the voltage on the ea+ pin is equal to the voltage on the soft pin minus the ?droop? resistor voltage, v droop . during start-up, when the voltage on soft is less than the ?boot? voltage v boot , a 130a current source i1, is used to slowly ramp up the voltage on the soft-start capacitor c soft . this slowly ramps up the reference voltage for the controller, and controls the slew rate of the output voltage. the stv pin is externally programmable and sets the start-up or ?boot? voltage v boot . the programming of this voltage level is explained in ?stv, dsv and drsv? on page 12. the ISL6218 pgood pin is both an input and an output. the system signal imvp4_pwrgd is connected to power good signals from the vccp and vcc_mch supplies. the intersil isl6225 dual voltage regulator is an ideal choice for the vccp and vcc_mch supplies. refer to figure 2 and figure 4. once the output voltage is within the ?boot? level regulation limits and a logic high pgood signal from the vccp and vccp_mch regulators is received, the ISL6218 is enabled to capture the vid code and regulate to that command voltage. the ?droop? current source i droop , is proportional to load current. this current source is used to reduce the reference voltage on ea+ by the voltage drop across the ?droop? resistor. a more in-depth explanation of ?droop? and the sizing of this resistor can be found in ?droop compensation? on page 14. figure 2. timing diagram showing vr_on, vcc_ core and pgood for vcc_core, vccp and vcc_mch vid vr_on/en v cc-core pgood vccp/vcc-mch pgood vcc-core <3ms -12% t1 3ms to 12ms >10s t2 capture vid code v boot v vid ISL6218
9 fn9101.6 august 6, 2007 the choice of value for soft-start capacitor is determined by the maximum slew rate required for the application. an example calculation is shown in equation 1. using the i 1 current source on the soft pin as 130a, and the slew rate of (10mv/ s), the soft capacitor is calculated in equation 1: gate drive signals the ISL6218 provides internal gate drive for a single channel, synchronous buck, core regulator. the ISL6218 was designed with a 4a, low side gate current sink ability, and a 2a, low-side gate current source ability to efficiently drive the latest, high performance mosfets. this feature will provide the system designer with flexibility in mosfet selection as well as optimum efficiency during all modes of operation. frequency setting the power channel switching frequency is set up by a resistor from the fset pin to ground. the choice of fset resistance for a desired switching frequency can be approximated using figure 3. the switching frequency is designed to operate between 250khz and 500khz per phase. core voltage programming the voltage identification pins (vid0, vid1, vid2, vid3, vid4 and vid5) set the dac output voltage. these pins do not have internal pull-up or pull-down capability. these pins will recognize 1.0v, 3.3v or 5. 0v cmos logic. table 1 shows the command voltage, v dac for the 6 bit vid codes. the ic responds to vid code changes as shown in figure 5. pgood is masked between these transitions. f 012 . 0 mv 10 s 1 a 130 slewrate i c source soft ? = = (eq. 1) figure 3. channel switching frequency vs r fset 250k 500k 750k 1m 0 50 100 150 200 250 channel switching frequency, f sw (hz) fset resistor value (k ) table 1. intel impv-iv vid codes vid5 vid4 vid3 vid2 vid1 vid0 v dac 0 0 0 0 0 0 1.708 0 0 0 0 0 1 1.692 0 0 0 0 1 0 1.676 0 0 0 0 1 1 1.660 0 0 0 1 0 0 1.644 0 0 0 1 0 1 1.628 0 0 0 1 1 0 1.612 0 0 0 1 1 1 1.596 0 0 1 0 0 0 1.580 0 0 1 0 0 1 1.564 0 0 1 0 1 0 1.548 0 0 1 0 1 1 1.532 0 0 1 1 0 0 1.516 0 0 1 1 0 1 1.500 0 0 1 1 1 0 1.484 0 0 1 1 1 1 1.468 0 1 0 0 0 0 1.452 0 1 0 0 0 1 1.436 0 1 0 0 1 0 1.420 0 1 0 0 1 1 1.404 figure 4. soft-start tracking circuitry showing internal current sources and ?droop? for active, deep and deeper sleep modes of operation c soft soft ea+ r droop ISL6218 i droop + v droop + error amplifier ISL6218
10 fn9101.6 august 6, 2007 active, deep sleep and deeper sleep modes the ISL6218 single-phase controller is designed to control the core output voltage as per the imvp-iv ? specifications for active, deep sleep, and deeper sleep modes of operation. after initial start-up, a logic high signal on dsen and a logic low signal on drsen signals the ISL6218 to operate in active mode (refer to table 2). this mode will recognize vid code changes and regulate the output voltage to these command voltages. a logic low signal present on stpcpu (pin dsen ), with a logic low signal on dprslpvr (pin drsen) signals the ISL6218 to reduce the core output voltage to the deep sleep level, the voltage on the dsv pin. a logic high on dprslpvr (pin drsen), with a logic low signal on stpcpu (pin dsen ), signals the ISL6218 controller to further reduce the core output voltage to the deeper sleep level, which is the voltage on the drsv pin. deep sleep and deeper sleep voltage levels are programmable and are explained in ?stv, dsv and drsv? on page 12. vid5 vid4 vid3 vid2 vid1 vid0 v dac 010100 1.388 010101 1.372 010110 1.356 010111 1.340 011000 1.324 011001 1.308 011010 1.292 011011 1.276 011100 1.260 011101 1.244 011110 1.228 011111 1.212 100000 1.196 100001 1.180 100010 1.164 100011 1.148 100100 1.132 100101 1.116 100110 1.100 100111 1.084 101000 1.068 101001 1.052 101010 1.036 101011 1.020 101100 1.004 101101 0.988 101110 0.972 101111 0.956 110000 0.940 110001 0.924 110010 0.908 110011 0.892 110100 0.876 110101 0.860 110110 0.844 110111 0.828 111000 0.812 111001 0.796 111010 0.780 111011 0.764 table 1. intel impv-iv vid codes (continued) vid5 vid4 vid3 vid2 vid1 vid0 v dac 1 1 1 1 0 0 0.748 1 1 1 1 0 1 0.732 1 1 1 1 1 0 0.716 1 1 1 1 1 1 0.700 table 2. output voltage as a function of dsen and drsen logic states dsen - stp _cpu drsen - dprslpvr mode of operation output voltage 1 0 active vid 0 0 deep sleep dsv 0 1 deeper sleep drsv 1 1 deeper sleep drsv table 1. intel impv-iv vid codes (continued) ISL6218
11 fn9101.6 august 6, 2007 deep sleep enable (dsen) and deeper sleep enable (drsen) table 2 shows logic states controlling modes of operation figure 6 and figure 5 show the timing for transitions entering and exiting deep sleep mode and deeper sleep mode, controlled by the syst em signals stpcpu and dprslpvr. pins dsen (deep sleep enable ) and drsen (deeper sleep enable) of the ISL6218 are connected to these 2 signals, respectively. for the case when dsen is logic high, and drsen is logic low, the controller will operate in active mode and regulate the output voltage to the vid commanded dac voltage minus the voltage ?droop? as determined by the load current. voltage ?droop? is the reduction of output voltage proportional to output current. when a logic low is seen on the dsen and drsen is logic low the controller will then regulate the output voltage to the voltage seen on the dsv pin minus ?droop?. when dsen is logic low and drsen is logic high the controller will operate in deeper sleep mode. the ISL6218 will then regulate to the voltage seen on the drsv pin minus ?droop?. deep and deeper sleep voltage levels are programmable and explained in ?stv, dsv and drsv? on page 12. discontinuous operation - psi the ISL6218 single-phase pwm controller is a synchronous buck regulator. however, in deep and deeper sleep modes where the load current is low, the controller operates as a standard buck regulator. this mode of operation acts to eliminate negative inductor current by truncating the low side mosfet gate drive pulse, and figure 5. plot showing timing of vid code changes and core voltage slewing as well as pgood masking figure 6. core voltage slewing to 98.8% of prog rammed vid voltage for a logic level low on dsen figure 7. vcore response for deeper sleep command new vid code new voltage level current voltage level vid[0..5] current vid code <600ns pgood high v cc_core v cc_core vid[0..5] vid code remains the same stp _cpu (dsen ) vid command voltage v deep sleep <3s vid code remains the same vid[0..5] stp_cpu (dsen ) deeper sleep dprslpvr (drsen) v cc_core v deep v deeper short dprslp causes v cc_core to ramp-up ISL6218
12 fn9101.6 august 6, 2007 shutting off the low side mosfet. this ?three-state? mode will hold both upper and low side mosfets off during the time that the low side mosfet would normally be on. this ?diode emulation? is initiated when the current, as sensed through the low side mosfet, is negative. this event triggers the ?three-state? mode until the next pwm cycle. this discontinuous operation impr oves efficiency by preventing the reverse conduction of current through the low side mosfet. this eliminates conduction loss and output discharge. discontinuous operation is enabled in deep and deeper sleep modes and is based solely on current feedback. due to this ISL6218?s ability to sense zero current and prevent discharging through the low side mosfets during light loads, the ISL6218 meets the requirements for psi without requiring any external signals. stv, dsv and drsv start-up ?boot? voltage - stv the start-up, or ?boot,? voltage is programmed by an external resistor divider network from the ocset pin (refer to figure 8). internally, a 1. 75v reference voltage is output on the ocset pin. the start-up voltage is set through a voltage divider from the 1.75v reference at the ocset pin. the voltage on the stv pin will be the controller regulating voltage during the start-up sequence. once the pgood pin of the isl6 218 controller is externally enabled high by the vccp and vcc_mch controllers, the ISL6218 will then ramp, after a 10s delay, to the voltage commanded by the vid setting minus ?droop?. deep sleep voltage- dsv the deep sleep voltage is programmed by an external voltage divider network from the dacout pin (refer to figure 8). the dacout pin is th e output of the vid digital- to-analog converter. by having the deep sleep voltage setup from a resistor divider from dac, the deep sleep voltage will be a constant percentage of t he vid. through the voltage divider network, deep sleep voltage is set to 98.8% of the programmed vid voltage, as per the imvp-iv ? specification. the ic enters the deep sleep mode when the dsen is low and the drsen pin is low as shown in figure 6 and figure 5. once in deep sleep mode, the controller will regulate to the voltage seen on the dsv pin minus ?droop?. deeper sleep voltage - drsv the deeper sleep voltage, drsv, is programmed by an external voltage divider network from the 1.75v reference on the ocset pin (refer to figure 8). in deeper sleep mode the ISL6218 controller will regulate the output voltage to the voltage present on the drsv pin minus ?droop?. the ic enters deeper sleep mode when drsen is high and dsen is low, as shown in figure 5. overcurrent setting - ocset the ISL6218 overcurrent protec tion essentially compares a user-selectable overcurrent threshold to the scaled and sampled output current. an overcurrent condition is defined when the sampled current is equal to or greater than the threshold current. a step by step process to the user-desired overcurrent set point is detailed next. step 1: setting the overcurrent threshold the overcurrent threshold is represented by the dc current flowing out of the ocset pin (see figure 8). since the ocset pin is held at a constant 1.75v, the user need only populate a resistor from this pin to ground to set the desired overcurrent threshold, i ocset . the user should pick a value of i ocset between 10a and 15a. once this is done, use ohm?s law to determine the necessary resistor to place from ocset to ground: for example, if the desired overcurrent threshold is 15a, the total resistance from ocset must equal 117k . step 2: selecting isen resistance for desired overcurrent level after choosing the i ocset level, the user must then decide what level of total output curr ent is desired for overcurrent. typically, this number is between 150% and 200% of the maximum operating current of t he application. for example, if the max operating current is 27a, and the user chooses 150% overcurrent, the ISL6218 will shut down if the output current exceeds 27a*1.5 or 40a. according to the ?block diagram? on page 7, equation 3 should be used to determine r isen once the overcurrent level, i oc , is chosen. figure 8. configurations for battery input, overcurrent setting and start, deep sleep and deeper sleep voltage ISL6218 battery v ref = 1.75v i ocset 36.5k 1.200v 30.1k 0.750v 49.9k ocset stv drsv soft gnd dsv dacout vbat 0.012f vid command voltage 1.21k 98.8% dacout 98.8k r1 r2 r3 (eq. 2) 3 2 1 ocset ocset r r r i v 75 . 1 r + + = = ISL6218
13 fn9101.6 august 6, 2007 in equation 3, m represents the number of low-side mosfets. using the examples above (i oc = 40a, i ocset = 15a) and substituting the values m = 2, r ds(on) = 4.5m , r isen is calculated to be 1370 . step 3: thermal compensation for r ds(on) (if desired) if ptcs are used for thermal compensation, then r isen is found using the room temperature value of r ds(on) . if standard resistors are used fo r risen, then the ?hot? value of r ds(on) should be used for this calculation. mosfet r ds(on) sensing provides advantages in cost, efficiency, and board area. however, if more precise current feedback is desired, a discrete precision current sense resistor r power may be inserted between the source of each channel?s lower mosfet and ground. the small r isen resistor, as previously described, is then replaced with a standard 1% resistor and connec ted from the is en pin of the ISL6218 controller to the source of the lower mosfet. battery feed-forward compensation - vbat as shown in figure 8, the ISL6218 incorporates battery voltage feed-forward compensation. this compensation provides a constant pulse width modulator gain independent of battery voltage. an understanding of this gain is required for proper loop compensation. the battery voltage is connected directly to the ISL6218 by the vbat pin, and the gain of the system ramp modulator is a constant 6.0. fault protection the ISL6218 protects the cpu from damaging stress levels. the overcurrent trip point is integral in preventing output shorts of varying degrees from causing current spikes that would damage a cpu. the output overvoltage and undervoltage detection features insure a safe window of operation for the cpu. output voltage monitoring vsen is connected to the local core output voltage and is used for pgood, undervoltage and overvoltage sensing only. (refer to the ?block diagram? on page 7). the vsen voltage is compared with two voltage levels that indicate an overvoltage or undervoltage condition of the output. violating either of these conditions results in the pgood pin toggling low to indicate a problem with the output voltage. pgood as previously described, the ISL6218 pgood pin operates as both an input and an outp ut. during start- up, the pgood pin operates as an input. refer to figure 9. as per the imvp-iv ? specification, once the ISL6218 core regulator regulates to the ?boot? voltage, it waits for the pgood logic high signals from the vccp and vcc_mch regulators. the intersil isl6225 is a perfect choice for these two supplies as it is a dual regulator and has independent pgood functions for each supply. once these two supplies are within regulation, pgood vccp and pgood vcc_mch will be high impedance, and will allow the pgood of the ISL6218 to sink approximately 2.6ma to ground through the internal mosfet, shown in figure 9. the ISL6218 detects this current and starts an internal pgood timer. the current sourced into the pgood pin is critical for proper start-up operation. the pullup resistor, r pull-up is sized to give a minimum of 2.6ma of current sourced into the pgood pin from 3.3v supply. as given in the ?electrical specifications? table on page 4, the pgood mosfet r ds(on) is given as 82 maximum. if a 3.3v source is used as the pull-up, then the pull-up resistor is given equation 4: where v source is the supply minus 5% for tolerance. this will insure that the required pgood current will be sourced into the pgood pin for worst case conditions of low supply and largest mosfet r ds(on) . once the proper level of pgoo d current is detected, the ISL6218 then captures the vid an d regulates to this value. the pgood timer is a function of the internal clock and switching frequency. the internal pgood delay can be calculated in equation 5: (eq. 3) 130 a 2 i 2175 . 0 m r i r ocset ) dson ( oc isen ? ? ? ? = figure 9. internal pgood circuitry for the ISL6218 core voltage regulator ~100ns t q q set clr s r start cpu -up = uv and ov start rst 3.3v pgood pgood vccp 1.2k 10k 3.3v 3ms to 12ms t ipgt isl6225 3.3v imvp4_pwrgd ISL6218 pgood clk _enable 10k vccp_m c (eq. 4) () () 1.2k ? 82 2.6ma 3.3 0.05 3.3 max dson r 2.6ma source v pullup r = ? ? = ? = (eq. 5) pgood timer delay = 3072 / f sw ISL6218
14 fn9101.6 august 6, 2007 the ISL6218 controller regulates the core output voltage to the vid command and once the timer has expired, the pgood output is allowed to go high. note, the pgood functions of the v cc_core , vccp and vcc_mch regulators are wire o r?d together to create the system signal ?imvp4_pwrgd?. if any of the supplies fall outside the regulation window, their respective pgood pins are pulled low, which forces imvp4_pwrgd low. pgood of the ISL6218 is internally disabled during all vid and mode transitions. overvoltage the vsen voltage is compared with an internal overvoltage protection (ovp) reference set to 112% of the vid voltage. if the vsen voltage exceeds the o vp reference, a comparator simultaneously sets the ov latch and triggers the pwm output low. the drivers turn on the lower mosfets, shunting the converter output to ground. once the output voltage falls below 102% of the set point, the high side and low side pwm outputs are held in ?three-state?. this prevents dumping of the output capacitors back through the output inductors and lower mosfets, which would cause a negative voltage on the core output. this architecture eliminates the need of a high current, schottky diode on the output. if the overvoltage conditions persist, the pwm outputs are cycled between output low and output ?off?, similar to a hysteretic regulator. the ov latch is reset by cycling the vdd supply voltage to initiate a por. depending on the mode of operation, the overvoltage setpoint is 112% of the vid, deep or deeper sleep setpoint. undervoltage the vsen pin is also compared to an undervoltage (uv) reference, which is set to 84% of the vid, deep or deeper sleep setpoint, depending on the mode of operation. if the vsen voltage is below the uv reference for more than 32 consecutive phase clock cycles, the power good monitor triggers the pgood pin to go low and latches the chip off until power is reset to the chip or the en pin is toggled. overcurrent the r isen resistor scales the voltage sampled across the lower mosfet and provides current feedback i sen , which is proportional to the output current (refer to figure 10). after current sensing function, i sen is obtained (refer to the ?block diagram? on page 7 and figure 10). i sen is compared with an internally generated overcurrent trip threshold that is propotional to the current sourced from the ocset pin, i ocset . the overcurrent trip current source is programmable and described in ?overcurrent setting - ocset? on page 12. if i sen exceeds the i ocset level, an up/down counter is enabled. if i sen ? does not fall below i ocset within 32 phase cycle counts, the pgood pin transitions low and latches the chip off. if normal operation resumes within the 32 phase cycle count window, the controlle r will continue to operate normally. note: due to ?droop?, there is inherent current limit since load current cannot exceed the amount that would command an output voltage lower than 84% of the vid voltage. this would result in an undervoltage shutdown and would also cause the pgood pin to transiti on low and latch the chip off. control loops figure 10 shows a simplified diagram of the voltage regulation and current control loops for a single-phase converter. both voltage and current feedback are used to precisely regulate voltage and tightly control output current i l1 . the voltage loop is comprised of the error amplifier, comparators, internal gate drivers and mosfets. the error amplifier drives the modulator to force the fb pin to the imvp-iv ? reference minus ?droop?. voltage loop the output core voltage feedback is applied to the error amplifier through the compensation network. the signal seen on the fb pin will drive the error amplifier output either high or low, depending upon the core voltage. a core voltage level that is lower than the imvp-iv ? reference, as output from the 6-bit dac, c auses the amplifier output to move towards a higher output voltage level. the amplifier output voltage is applied to the positive input of the comparator. increasing error am plifier voltage results in increased comparator output dut y cycle. this increased duty cycle signal is passed through th e pwm circuit to the internal gate drive circuitry. the output of the internal gate drive is directly connected to the gate of the mosfets. increased duty cycle, or on-time, for the high side mosfet transistors, results in increased output voltage (vcore) to compensate for the low output voltage sensed. droop compensation microprocessors and other peripherals tend to change their load current demands from near no-load to full load, often during operation. these same devices require minimal output voltage deviation during a load step. a high di/dt load step will cause an output voltage spike. the amplitude of the spike is dictated by the output capacitor esr multiplied by the load st ep magnitude plus the output capacitor esl times the load step di/dt. a positive load step produces a negative output voltage spike and vice versa. a large number of low-series-im pedance capacitors are often used to prevent the output voltage deviation from exceeding the tolerance of some devices. one widely accepted solution to this problem is output voltage ?droop?, or active voltage positioning. as shown in the block diagram, the sensed current (i sen ) is used to control the ?droop? current source, i droop . the ?droop? current source is a controlled current source and is proportional to output current. this current source is ISL6218
15 fn9101.6 august 6, 2007 approximately ? of the i sen , as shown in the ?block diagram? on page 7. the droop current is sourced out of the soft pin through the droop resistor and returns through the ea+ pin. this creates a ?droop? voltage v droop , that subtracts from the imvp-iv ? reference voltage on soft to generate the voltage setpoint for the core regulator. full load current for the intel imvp-iv ? thin and light specification is 25a. knowin g that the droop current, sourced out of the soft pin will be ? of the i sen , a ?droop? resistor, r droop , can be selected to provide the amount of voltage ?droop? required at full load. the selection of this resistor is explained ?selection of rdroop? on page 15. selection of r droop figure 11 shows a static ?droop? load line for the 1.484v active mode. the ISL6218, as pr eviously mentioned, allows the programming of the load lin e slope by the selection of the r droop resistor. as per the intel imvp-iv ? and imvp-iv+ ? specification, droop = 0.003 ( ). therefore, 25a of full load current equates to a 0.075v droop out put voltage from the vid setpoint. r droop can be selected based on r isen which is calculated through equation 3, r (ds(on) and droop, as per the ?block diagram? on page 7 or equation 6: component selection guidelines output capacitor selection output capacitors are required to filter the output inductor current ripple, and supply the transient load current. the filtering requirements are a f unction of the channel switching frequency and the output ripple current. the load transient requirements are a function of th e slew rate (di/dt) and the magnitude of the transi ent load current. the microprocessor used for imvp-iv ? will produce transient load rates as high as 30a/ns. high frequency ceramic capacitors are used to supply the initial transient current, and slow the rate-of-change seen by t he bulk capacitors. bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements, rather than actual capacitanc e requirements. to meet the stringent requirements of imvp-iv ? , (15) 2.2f, 0612 ?flip chip? high frequency, ceramic capacitors are placed very close c dcpl current sensing comparator pwm circuit r isen error amplifier comp reference isen1 v core ug1 ISL6218 c out r load q1 q2 l 01 phase i l1 v in + imvp iv - - + fb vsen r1 r2 c1 c2 v error1 lg1 ea+ soft c soft + - v rds(on) + - i droop v droop + _ current i ocset over voltage over-under v rds(on) r droop i sen1 i sen i sen ? figure 10. simplified block diagram of the ISL6218 vo ltage and current control l oops for the single channel regulator. (eq. 6) () ) ( m r r droop 3 . 2 r ) dson ( isen droop ? ? = figure 11. imvp-iv ? active mode static load line v out, hi v out, lo i out, max i out, nl v out, nom i out, mid -3m load line (25a, 1.409v) (0a, 1.506v) (0a, 1.484v) (25a, 1.431v) (0a, 1.462v) (25a, 1.387v) static tolerance bands nominal "droop" load line ISL6218
16 fn9101.6 august 6, 2007 to the processor power pins; they are placed carefully so they do not to add inductance in the circuit board traces, which could cancel the usefulness of these low inductance components. specialized low-esr capacitors intended for switching regulator applications are recommended for the bulk capacitors. the bulk capacitors esr and esl determine the output ripple voltage and the initial voltage drop following a high slew-rate transient edge. recommended are at least (4) 4v, 220f sanyo sp-cap capacitors in parallel, or (5) 330f sp-cap style capacitors. thes e capacitors provide an equivalent esr of less than 3m . these components should be laid out very close to the load. as the sense trace for vsen may be long and routed close to switching nodes, a 1.0f ceramic decoupling capacitor is located between vsen and ground at the ISL6218 package. output inductor selection the output inductor is selected to meet the voltage ripple requirements and minimize the converter response time to a load transient. the inductor selected for the power channel determines the channel ripple current. increasing the value of inductance reduces the total output ripp le current and total output voltage ripple, but will slow the converter response time to a load transient. one of the parameters limiting t he converter?s response time to a load transient is the time required to slew the inductor current from its initial current level to the transient current level. during this interval, the difference between the two levels must be supplied by the output capacitance. minimizing the response time can minimize the output capacitance required. the channel ripple current is approximated by equation 7: input capacitor selection use a mix of input bypass capaci tors to control the voltage overshoot across the mosfets. use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capacitors must be placed very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. two important parameters to consider when selecting the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select a bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. mosfet selection and considerations for the intel imvp-iv ? application that requires up to 20a of current, it is suggested that single-phase channel operation, with a minimum of (4) mosfets per channel, be implemented. this configuration would be: (2) high switching frequency, low gate charge mosfet for the upper; and (2) low r ds(on) mosfets for the lowers. in high-current pwm applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components: conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty cycle of the converter. refer to equations 8 and 9. the conduction losses are the main component of power dissipation for the lower mosfets. only the upper mosfets have significant swit ching losses, since the lower devices turn on and off into near zero voltage. the following equations assume linear voltage- current transitions and do not model power loss due to the reverse-recovery of the lowe r mosfet?s body diode. the gate-charge losses are dissipated in the ISL6218 drivers and do not heat the mosfets; however, large gate-charge increases the switching time t sw , which increases the upper mosfet switching losses. ensu re that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. typical application - single phase converter using ISL6218 pwm controller figure 12 shows the ISL6218, synchronous buck converter circuit, which is used to provide the core voltage regulation for the intel imvp-iv ? application. the circuit uses a single power channel to deliver up to 20a steady state current, and has a 330khz channel switching frequency. for thermal compensation, a ptc resistor is used as sense resistors. the output capacitance is less than 3m of esr and is (4) 220f, 4v sp-cap parts in parallel with (35) high frequency, 10f ceramic capacitors. (eq. 7) in out sw out in ch v v l f v v i ? ? ? = (eq. 8) () 2 f t v i v v r i p sw sw in o in out on ds 2 o upper + = (eq. 9) () () in out in on ds 2 o lower v v v r i p ? = ISL6218
17 fn9101.6 august 6, 2007 figure 12. typical application circuit for the ISL6218, imvp-iv ? core voltage regulator analog power vdd dacout dsv fset en drsen dsen vid0 vid1 vid2 vid3 vid4 vid5 pgood ea+ comp fb soft vbat isen phase ug boot vssp lg vddp vsen drsv stv ocset vss 0.012f 4 x 220f 35 x 10f 2 x si4362dy 2 x irf7811w 0.8h etq-p3h0r8ba vr_on dpslp vid vbattery +5vdc +5vdc +vcc_core 36.5k_1% 30.1k_1% 49.9k_1% 8 x 10f 1.5k_1%ptc 3.57k_1% 14k_1% 3300pf 4.64k_1% 1f 1.2k__1% 174k_1% 4.7f 1800pf no-pop no-pop 560pf 0.33f 10_1% 1r5_5% 0.027f bat54 nc nc nc nc nc nc nc ISL6218 tssop 98.8k__1% and ISL6218
18 fn9101.6 august 6, 2007 ISL6218 package outline drawing l40.6x6 40 lead quad flat no-lead plastic package rev 3, 10/06 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (4x) 0.15 index area pin 1 a 6.00 b 6.00 31 36x 0.50 4.5 4x 40 pin #1 index area bottom view 40x 0 . 4 0 . 1 20 b 0.10 11 ma c 4 21 4 . 10 0 . 15 0 . 90 0 . 1 c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. detail "x" 0 . 05 max. 0 . 2 ref c 5 side view 1 10 30 typical recommended land pattern ( 5 . 8 typ ) ( 4 . 10 ) ( 36x 0 . 5 ) ( 40x 0 . 23 ) ( 40x 0 . 6 ) 6 6 top view 0 . 23 +0 . 07 / -0 . 05
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9101.6 august 6, 2007 ISL6218 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-bd-1, issue f. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m38.173 38 lead thin shrink small outline plastic package (compliant to jedec mo-153-bd-1 issue f) symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0106 0.17 0.27 9 c 0.0035 0.0079 0.09 0.20 - d 0.378 0.386 9.60 9.80 3 e1 0.169 0.177 4.30 4.50 4 e 0.0197 bsc 0.500 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n38 387 0 o 8 o 0 o 8 o - rev. 0 1/03

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